| capability | |||
| Technical Specification | Remark | ||
| Layer | 1~16 | ||
| Finished Board Thickness | 0.40 mm-3.20 mm (16 mil- 128mil) | ||
| Min core material thickness | 0.1mm (4 mil) | ||
| Copper thickness | min: 1/3 oz (base), max: 4 oz (finished) | ||
| Min line width/space | Double side | 0.075 mm ( 3 mil )-Hoz | |
| Multi-layer | 0.075 mm ( 3 mil )-Hoz | ||
| Min hole size | Drilling hole | φ0.2 mm ( 8mil, drill bit ) | |
| Punch hole | φ0.80 mm ( 32 mil ) | ||
| Tolrance | Hole location Tolrance | ± 0.075 mm ( 3 mil ) | |
| Circuit width Tolrance | ± 20%(Nomal) or ± 10%(Special control) | ||
| Hole size | NPTH: ± 0.03 mm ( 1.2 mil ) | ||
| PTH: ± 0.076mm(3mil Normal) or ±0.05 mm(2mil Special) | |||
| Outline Tolerance | ± 0.10 mm ( 4 mil ) | ||
| Circuit to edge Tolerance | ± 0.15 mm ( 6 mil ) | ||
| Warpage | ≤0.75%(Normal) or ≤0.5%(Special control) | ||
| Surface treatment | Immersion
Au/Silver/Tin OSP/LF-HASL | Carbon ink, Peelable mask | |
| V-Cut | Min board Thickness | 0.40 mm (16mil) | |
| Min remain Thickness | 0.20 mm (8mil) | ||
| Tolerance | ± 0.1 mm (4mil) | ||
| Min space between hole edge and circuit | PTH hole: 0.13mm (5mil) | ||
| NPTH hole: 0.18mm (7mil) | |||
| Position Tolerance between circuit and hole | Circuit to hole | ± 0.075mm (3mil) | |
| Circuit to the second drill hole | ± 0.10mm (4mil) | ||
| Position Tolerance of circuit between different layers | (relative position between top and bottom circuit) | 0.075mm (3mil) | |
| Multilayer | Min space between circuit and edge of inner layer | 0.225mm (9mil) | |
| Min board thickness | 4 layers: 0.35mm (14mil) | ||
| 6 layers: 0.65mm (26mil) | |||
| 8 layers: 1.00mm (40mil) | |||
| 10 layers: 1.30mm (51mil) | |||
| 12 layers: 1.60mm (63mil) | |||
| Board thickness tolerance | 4 layers: +/-0.13mm (5mil) | ||
| 6 layers: +/-0.13mm (5mil) | |||
| 8 layers: +/-0.15mm (6mil) | |||
| 10 layers: +/-0.15mm (6mil) | |||
| 12 layers: +/-0.20mm (8mil) | |||
| Impedance Control Tolerance | +/-10% | ||